Publications by type

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Book chapters

• Toshinori Sato, Itsujiro Arita, Constructive Timing Violation for Improving Energy Efficiency, in Luca Benini, Mahmut Kandemir, J. Ramanujam, Compilers and Operating Systems for Low Power, Kluwer Academic Publishers, pp.137-153, September 2003.

Journal articles

• Toshinori Sato, Akihiro Chiyonobu, An Energy-Efficient Clustered Superscalar Processor, IEICE Transactions on Electronics, Vol. E88-C, No. 4, pp.544-551, April 2005.
• Toshinori Sato, Exploiting Sub-word Parallelism for Dependable Processors, WSEAS Transactions on Information Science and Applications, Vol. 1, No. 6, pp.1051-1056, December 2004.
• Koichiro Tanaka, Yuhei Hayashi, Sunao Sawada, Toshinori Sato, Itsujiro Arita, Embedded System Design Education Using an FPGA/DSP-Based System, IEICE Transactions on Electronics, Vol. J87-D1, No.6, pp.640-648, June 2004 (in Japanese).
• Takenori Koushiro, Toshinori Sato, A Low-Cost Value Predictor for Energy-Efficient Speculative Multithreaded Processors, IPSJ Transactions on Advanced Computing Systems, Vol. 45, No. SIG 1(ACS 4), pp.43-53, January 2004 (in Japanese).
• Toshinori Sato, A Transparent Transient Faults Tolerance Mechanism for Superscalar Processors, IEICE Transactions on Information and Systems, Vol. E86-D, No. 12, pp.2508-2516, December 2003.
• Toshinori Sato, Itsujiro Arita, Combining Variable Latency Pipeline with Instruction Reuse for Execution Latency Reduction, Systems and Computers in Japan, Vol. 34, No. 12, pp.11-21, November 2003.
• Akihiro Chiyonobu, Toshinori Sato, Itsujiro Arita, An Evaluation of Critical Path Predictors for Low Power Processor Architecture, IEICE Transactions on Electronics, Vol. J86-C, No. 8, pp.826-835, August 2003 (in Japanese).
• Toshinori Sato, Itsujiro Arita, Combining Variable Latency Pipeline with Instruction Reuse for Execution Latency Reduction, IEICE Transactions on Information and Systems, Vol. J85-D-I, No. 12, December 2002 (in Japanese).
• Toshinori Sato, Kiichi Sugitani, Akihiko Hamano, Itsujiro Arita, Evaluating Influence of Compiler Optimizations on Data Speculation, Journal of Information Science and Engineering, Vol. 18, No. 6, pp.1027-1036, November 2002.
• Toshinori Sato, Itsujiro Arita, Potential of Constructive Timing-Violation, IEICE Transactions on Electronics, Vol. E85-C, No. 2, pp.323-330, February 2002.
• Toshinori Sato, Evaluating the Impact of Reissued Instructions on Data Speculative Processor Performance, Microprocessors and Microsystems, Vol. 25, No. 9-10, pp.469-482, January 2002.
• Toshinori Sato, Toshiyuki Yamamoto, Itsujiro Arita, The KIT COSMOS Processor: A Low-Complexity Superscalar Processor, International Journal of Computer & Information Science, Vol. 2, No. 4, pp.182-190, December 2001.
• Toshinori Sato, Evaluating Trace Cache on Moderate Scale Processors, IEE Proceedings on Computers and Digital Techniques, Vol. 147, No. 6, pp.369-374, November 2000.
• Toshinori Sato, Quantitative Evaluation of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism, Journal of Systems Architecture, Vol. 46, No. 13, pp.1231-1252, November 2000.
• Nobuhiro Ide, Masashi Hirano, Yukio Endo, Shin'ichi Yoshioka, Hiroaki Murakami, Atsushi Kunimatsu, Toshinori Sato, Takayuki Kamei, Toyoshi Okada, Masakazu Suzuoki, 2.44 GFLOPS 300MHz Floating-Point Vector Processing Unit for High Performance 3D Graphics Computing, IEEE Journal of Solid-State Circuits, Vol. 35, No. 7, pp.1025-1033, July 2000.
• Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki, Vector Units Architecture for Emotion Synthesis, IEEE Micro, Vol. 20, No. 2, pp.40-47, March/April 2000.
• Toshinori Sato, A Simulation Study of Combining Load Value and Address Predictors, International Journal of High Speed Computing, Vol. 10, No. 3, pp.301-325, September 1999.
• Toshinori Sato, Load Value Prediction via Two-hop Reference Address Renaming, Transactions of IPSJ, Vol. 40, No. 5, pp.2109-2118, May 1999 (in Japanese). Bast Paper Award of IPS Japan
• Toshinori Sato, Improving Efficiency of Dynamic Speculation via Data Address Prediction Using Instruction Reissue Mechanism, Transactions of IPSJ Vol. 40, No. 5, pp.2093-2108, May 1999 (in Japanese).
• Toshinori Sato, A Microprocessor Architecture Utilizing Histories of Dynamic Sequences Saved in Distributed Memories, IEICE Transactions on Electronics, Vol. E81-C, No. 9, pp.1398-1407, September 1998.
• Toshinori Sato, Resolving Load Data Dependency using Tunneling-Load Technique, IEICE Transactions on Information and Systems Vol. E81-D, No. 8, pp.829-838, August 1998.
• Toshinori Sato, Aliasing-Free Pattern History Table for Two-Level Adaptive Branch Predictors, Tranactions of IEICE D-I Vol. J81-D-I, No. 6, pp.728-737, June 1998 (in Japanese).
• Toshinori Sato, Hiroshige Fujii, Seigo Suzuki, Hiding Data Cache Latency with Load Address Prediction, IEICE Transactions on Information and Systems, Vol. E79-D, No. 11, pp.1523-1532, November 1996.
• Masato Nagamatsu, Toshinori Sato, Haruyuki Tago, R3900 High-Performance and Low-Power-Comsumption Processor, Toshiba Review, Vol. 50, No.12, pp,883-886, December 1995 (in Japanese).
• Masafumi Takahashi, Hiroshige Fujii, Emi Kaneko, Takeshi Yoshida, Toshinori Sato, Hiroyuki Takano, Haruyuki Tago, Seigo Suzuki, Nobuyuki Goto, Performance Evaluation of a Processing Element for an On-Chip Multiprocessor, IEICE Transactions on Electronics, Vol. E77-C, No. 7, pp.1092-1100, July 1994.
• Nobuhiro Ide, Hiroto Fukuhisa, Hiroyuki Takano, Takeshi Yoshida, Toshinori Sato, Haruyuki Tago, A 320 MFLOPS CMOS Floating-point Processing Unit for Superscalar Processors, IEEE Denshi Tokyo, No. 32, pp.104-109, 1993.
• Ryosuke Okuda, Toshinori Sato, Hidetoshi Onodera, Keikichi Tamaru, An Algorithm for Layout Compaction Problem with Symmetry Constraints, Tranactions of IEICE A, Vol. J73-A, No. 3, pp.536-543, March 1990 (in Japanese).

Conference papers

• Takahiro Kawahara, Koichiro Tanaka, Toshinori Sato, Implementation of a Controller for an FPGA Allowing Dynamic and Partial Reconfiguration on FPGA/DSP Hardware Platform RICE, International Symposium on Advanced Reconfigurable Systems, December 2005.
• Akihiro Chiyonobu, Toshinori Sato, Energy-Efficient Instruction Scheduling Exploiting Memory Access Slack, Workshop on Memory Performance: Dealing with Applications, Systems, and Architecture (MEDEA) held in conjunction with 14th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp.67-74, September 2005.
• Yuichiro Imaizumi, Toshinori Sato, Folding Active List for High Performance and Low Power, 6th International Symposium on High Performance Computing (ISHPC), CD-ROM, September 2005.
• Toshinori Sato, Comparing Fault Recovery Mechanisms for Superscalar Processors, 6th International Conference on Dependable Systems and Networks (DSN), pp.74-75, June 2005.
• Hidenori Sato, Toshinori Sato, A Preliminary Evaluation on Energy Effciency of a Temperature-aware Multicore-processor, 2nd Workshop on Temperature Aware Computer Systems (TACS) held in conjunction with 32nd International Symposium on Computer Architecture (ISCA), June 2005.
• Toshinori Sato, Exploiting Trivial Computation in Dependable Processors, 20th International Conference on Computers and Their Applications (CATA), pp.168-173, March 2005.
• Takamasa Tokunaga, Toshinori Sato, Profiling with Helper Threads, International Conference on Parallel and Distributed Computing and Networks (PDCN), pp.1-6, February 2005.
• Toshinori Sato, Exploiting Sub-word Parallelism for Dependable Processors, 5th International Conference on Automation & Information (ICAI), CD-ROM, November 2004.
• Kazuhiro Mima, Toshinori Sato, Hardware Cost Reduction in Fault Detection Mechanism for Constructive Timing Violation Technique, 10th International Symposium on Integrated Circuits, Devices and Systems (ISIC), CD-ROM, September 2004.
• Akio Kodama, Toshinori Sato, A Non-Uniform Cache Architecture on Networks-on-Chip: A Fully Associative Approach with Pre-Promotion, 10th International Symposium on Integrated Circuits, Devices and Systems (ISIC), CD-ROM, September 2004.
• Seiichiro Fujii, Toshinori Sato Non-Uniform Set Associative Caches for Power-Aware Embedded Processors, International Conference on Embedded and Ubiquitous Computing (EUC), pp.217-226, August 2004.
• Akihiro Chiyonobu, Toshinori Sato, Exploring Configuration of Dual Speed Pipelines for Criticality-based Energy-efficient Processors, 8th World Multiconference on Systemics, Cybernetics and Informatics (SCI), Vol. II, pp.16-21, July 2004.
• Yuu Tanaka, Toshinori Sato, Takenori Koushiro, The Potential in Energy Efficiency of a Speculative Chip-Multiprocessor, 16th Symposium on Parallelism in Algorithms and Architectures (SPAA), pp.273-274, June 2004.
• Akihiro Chiyonobu, Toshinori Sato, Investigating Heterogeneous Combination of Functional Units for a Criticality-based Low-power Processor Architecture, 3rd International Symposium on Information and Communication Technologies (ISICT), pp.190-195, June 2004.
• Seiichiro Fujii, Akihiro Chiyonobu, Toshinori Sato, A Power-aware Cache Architecture Utilizing Data Criticality, Symposium on Advanced Computing Systems and Infrastructures (SACSIS), pp.123-124, May 2004 (in Japanese).
• Masaharu Goto, Toshinori Sato, Leakage Energy Reduction in Register Renaming, 1st International Workshop on Embedded Computing Systems (EC) held in conjunction with 24th International Conference on Distributed Computing Systems (ICDCS), pp.890-895, March 2004.
  
• Hidenori Sato, Toshinori Sato, A Static and Dynamic Energy Reduction Technique for I-Cache and BTB in Embedded Processors, Asia and South Pacific Design Automation Conference (ASP-DAC), pp.831-834, January 2004.
• Toshinori Sato, Daisuke Morishita, A Field-Customizable and Runtime-Adaptable Microarchitecture, 2nd International Conference on Field-Programmable Technology (FPT), pp.328-331, December 2003.
• Asami Tanino, Toshinori Sato, Simplifying High-Frequency Microprocessor Design via Timing Constraint Speculation, 16th International Conference on Computer Applications in Industry and Engineering (CAINE), pp.282-287, November 2003.
• Toshinori Sato, Exploiting Instruction Redundancy for Transient Fault Tolerance, 18th International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pp.547-554, November 2003.
• Akihiro Chiyonobu, Toshinori Sato, On Identifying Instruction Criticality for Energy-Aware Applications, 12th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2003.
• Akihito Sakanaka, Toshinori Sato, A Leakage-Energy-Reduction Technique for High-Associativity Caches in Embedded Systems, Workshop on Memory Access Decoupled Architectures and Related Issues (MEDEA) held in conjunction with 12th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp.51-56, September 2003.
• Asami Tanino, Toshinori Sato, Evaluating the Potential of an Energy Reduction Technique Based on Timing Constraint Speculation, 4th Workshop on Compilers and Operating Systems for Low Power (COLP) held in conjunction with 12th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2003.
• Akihito Sakanaka, Toshinori Sato, Reducing Static Energy of Cache Memories via Prediction-Table-less Way Prediction, 13th International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), pp.530-539, September 2003.
• Koichiro Tanaka, Yuich Iwaya, Yuhei Hayashi, Toshinori Sato, Itsujiro Arita, Design of SpecC-Based Hardware/Software Co-Design Enbironments, DA Symposium (DAS), pp.157-162, July 2003 (in Japanese).
• Kohtaro Hashimoto, Makoto Sakuragi, Koichiro Tanaka, Toshinori Sato, Itsujiro Arita, Design of Hardware/Software Co-Design Enbironments Based on Simlink, DA Symposium (DAS), pp.163-168, July 2003 (in Japanese).
• Yuhei Hayashi, Masatoshi Matsuyama, Koichiro Tanaka, Toshinori Sato, Itsujiro Arita, Analysis of Relation between Bit-Width and Structure of N-bit Arithmetic Units for New FPGA IP Generators, DA Symposium (DAS), pp.157-162, July 2003 (in Japanese).
• Yuhei Hayashi, Koichiro Tanaka, Toshinori Sato, Itsujiro Arita, Design of Hardware/Software Co-Design Emvironment Using SpecC-based Tools, International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Vol.3, pp.1599-1602, July 2003.
• Takenori Koushiro, Toshinori Sato, An Energy-Efficient Speculative Chip-Multiprocessor Utilizing Trace-level Value Prediction, 1st Value-Prediction Workshop (VPW1) held in conjunction with 30th International Symposium on Computer Architecture (ISCA), pp.79-85, June 2003.
• Akihiro Chiyonobu, Toshinori Sato, Itsujiro Arita, A Study on Specifying Critical Instructions for Energy Reduction, Symposium on Advanced Computing Systems and Infrastructures (SACSIS), pp.155-156, May 2003 (in Japanese).
• Jun Tachikawa, Kenichiro Fukuda, Takanori Hira, Yoshimasa Ohnishi, Toshinori Sato, Itsujiro Arita, A Task-based Parallel Processing Framework for Heterogeneous Clusters, Symposium on Advanced Computing Systems and Infrastructures (SACSIS), pp.193-194, May 2003 (in Japanese).
• Asami Tanino, Toshinori Sato, Itsujiro Arita, An Evaluation of Constructive Timing Violation via CSLA Design, 6th International Symposium on Low-Power and High-Speed Chips (COOL Chips), pp.74, April 2003.
• Akihiro Chiyonobu, Toshinori Sato, Itsujiro Arita, Correlation-based Critical Path Predictors for Low Power Microprocessors, 6th International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA), pp.11-18, January 2003.
• Kou Morita, Toshinori Sato, Itsujiro Arita, The KIT COSMOS Processor: A Preliminary Study on Transparent Software Prefetching via Dynamic Optimization, 6th Workshop on Multi-threaded Execution, Architecture and Compilation (MTEAC), held in conjunction with 35th International Symposium on Microarchitecture (MICRO), pp.11-18, November 2002.
• Toshinori Sato, Itsujiro Arita, Reducing Energy Consumption via Low-Cost Value Prediction, 12th International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), pp.380-389, September 2002.
• Toshinori Sato, Itsujiro Arita, Simplifying Instruction Issue Logic in Superscalar Processors, EUROMICRO Symposium on Digital System Design: Architectures, Methods and Tools (DSD), pp.341-346, September 2002.
• Koichiro Tanaka, Yuichi Iwaya, Yuhei Hayashi, Toshinori Sato, Itsujiro Arita, Design and Implementation of FPGA/DSP Based PCI Card, Workshop on Logic and Synthesis for Programmable Devices (WLSPD) held in conjunction with 15th International Conference on Systems Engineering (ICSEng), pp.19-24, August 2002.
• Toshiyuki Yamamoto, Kou Morita, Toshinori Sato, Itsujiro Arita, The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization, 2002 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), Vol. 2, pp.1010-1016, June 2002.
• Takenori Koushiro, Toshinori Sato, Itujiro Arita, Decoupled Trace-Level Value Predictor for Hardware Cost Reduction, 14th Joint Symposium on Parallel Processing (JSPP), pp.171-172, May 2002 (in Japanese).
• Toshinori Sato, Akihiro Chiyonobu, Itsujiro Arita, Energy Reduction via Critical Path Prediction, Workshop on Complexity-Effective Design (WCED) held in conjunction with 29th International Symposium on Computer Architecture (ISCA), May 2002.
• Toshinori Sato, Itsujiro Arita, Low-Cost Value Predictors Using Frequent Value Locality, 4th International Symposium on High Performance Computing (ISHPC), pp.106-119, May 2002.
• Toshinori Sato, Takenori Koushiro, Akihiro Chiyonobu, Itujiro Arita, Power and Performance Fitting in Nanometer Design, 5th International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA), pp.3-10, January 2002.
• Toshinori Sato, Itsujiro Arita, Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications, Pacific Rim International Symposium on Dependable Computing (PRDC), pp.225-232, December 2001.
• Toshinori Sato, Itsujiro Arita, Contrail Processors for Converting High-Performance into Energy-Efficiency, 10th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2001.
  
• Toshinori Sato, Itsujiro Arita, Constructive Timing Violation for Improving Energy Efficiency, 2nd Workshop on Compilers and Operating Systems for Low Power (COLP) held in conjunction with 10th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp.7.1-7.8, September 2001.
• Toshinori Sato, Itsujiro Arita, In Search of Efficient Reliable Processor Design, 30th International Conference on Parallel Processing (ICPP), pp.525-532, September 2001.
• Toshinori Sato, Itsujiro Arita, Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse, 7th International Euro-Par Conference (Euro-Par), pp.428-438, August 2001.
• Toshinori Sato, Toshiyuki Yamamoto, Itsujiro Arita, The KIT COSMOS Processor: Some Ideas on Realizing Complexity-Effective Superscalar Processors, 2nd International Conference on Software Engineering, Artificial Intelligence, Networking & Parallel/Distributed Computing (SNPD), pp.549-556, August 2001.
• Toshinori Sato, Itsujiro Arita, Tolerating Transient Faults through an Instruction Reissue Mechanism, 14th International Conference on Parallel and Distributed Computing Systems (PDCS), pp.240-247, August 2001.
• Toshinori Sato, Itsujiro Arita, Transient Faults Tolerance Mechanism for Microprocessors, 2nd International Conference on Dependable Systems and Networks (DSN), pp.B8-9, June 2001.
• Toshinori Sato, Yusuke Nakamura, Itsujiro Arita, Revisiting Direct Tag Search Algorithm on Superscalar Processors, Workshop on Complexity-Effective Design (WCED) held in conjunction with 28th International Symposium on Computer Architecture (ISCA), June 2001.
• Toshinori Sato, Akihiko Hamano, Kiichi Sugitani, Itsujiro Arita, Influence of Compiler Optimizations on Value Prediction, 9th International Conference on High Performance Computing and Networking Europe (HPCN), pp.312-321, June 2001.
• Jun Tachikawa, Daigo Kihara, Takeshi Fukuzawa, Koichiro Tanaka, Yoshimasa Ohnishi, Bernady O. Apduhan, Toshinori Sato, Itsujiro Arita, HR-net: A Switching Network Architecture for Highly Scalable Parallel Processing System, 13th Joint Symposium on Parallel Processing (JSPP), pp.111-112, June 2001 (in Japanese).
• Toshinori Sato, Itsujiro Arita, Tolerating Transient Faults in Microprocessors, 13th Joint Symposium on Parallel Processing (JSPP), pp.335-342, June 2001 (in Japanese).
• Toshinori Sato, Itsujiro Arita, Simplifying Wakeup Logic in Superscalar Processors, 13th Joint Symposium on Parallel Processing (JSPP), pp.23-30, June 2001 (in Japanese).
• Toshinori Sato, Itsujiro Arita, Give up Meeting Timing Constraints, but Tolerate Violations, 4th International Symposium on Low-Power and High-Speed Chips (COOL Chips), pp.141-146, April 2001.
• Toshiyuki Yamamoto, Toshinori Sato, Itsujiro Arita, The KIT COSMOS Processor: Eliminating Ineffectual Branch Instructions via Concurrent Dynamic Optimization, 4th International Symposium on Low-Power and High-Speed Chips (COOL Chips), pp.346, April 2001.
• Kiichi Sugitani, Akihiko Hamano, Toshinori Sato, Itsujiro Arita, Evaluating Effect of Optimization Level on Value Predictability, 4th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), pp.695-698, December 2000.
• Toshinori Sato, Itsujiro Arita, Comprehensive Evaluation of an Instruction Reissue Mechanism, 5th International Symposium on Parallel Architectures, Algorithms and Networks (I-SPAN), pp.78-85, December 2000.
• Toshinori Sato, Itsujiro Arita, Partial Resolution in Data Value Predictors, 29th International Conference on Parallel Processing (ICPP), pp.69-76, August 2000.
• Tomohiro Oohama, Koichiro Tanaka, Toshinori Sato, Itsujiro Arita, The Design of the Parallel Computer Using PC Clusters with Distributed Shared Memory, 2000 Symposium on Multimedia, Distributed, Cooperative and Mobile Systems (DICOMO), June 2000 (in Japanese).
• Toshinori Sato, Itsujiro Arita, The KIT COSMOS Processor: Introducing CONDOR, 2000 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), Vol.1, pp.73-739, June 2000.
• Yuhei Hayashi, Koichiro Tanaka, Toshinori Sato, Itsujiro Arita, Design of Parallel Processing Systems Using DSPs and CPUs, 12th Joint Symposium on Parallel Processing (JSPP), pp.169, May 2000 (in Japanese).
• Toshinori Sato, Itsujiro Arita, Reducing Hardware Budget of Data Value Predictors by Exploiting Narrow Bitwidth, 12th Joint Symposium on Parallel Processing (JSPP), pp.245-252, May 2000 (In Japanese).
• Toshinori Sato, Itsujiro Arita, Table Size Reduction for Data Value Predictors by Exploiting Narrow Width Values, 14th International Conference on Supercomputing (ICS), pp.196-205, May 2000.
• Takayuki Kamei, Hideki Takeda, Yukio Ootagro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shinichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Atsushi Kunimatu, 300MHz Design Methodology of VU for Emotion Synthesis, Asia and South Pacific Design Automation Conference (ASP-DAC), pp.635-640, January 2000.
• Nobuhiro Ide, Masashi Hirano, Yukio Endo, Shin'ichi Yoshioka, Hiroaki Murakami, Atsushi Kunimatsu, Toshinori Sato, Takayuki Kamei, Toyoshi Okada, Masakazu Suzuoki, 2.44 GFLOPS 300MHz Floating-Point Vector Processing Unit for High Performance 3D Graphics Computing, 25th European Solid-State Circuits Conference (ESSCIRC), pp.106-109, September 1999.
• Toshinori Sato, A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism, EUROMICRO Conference, Workshop on Digital System Design: Architectures, Methods and Tools (DSD), pp.178-185, September 1999.
• Toshinori Sato, Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure, 5th International Euro-Par Conference (Euro-Par), pp.1281-1290, August 1999.
• Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki, 5.5 GFLOPS Vector Units for Emotion Synthesis, Hot Chips 11, pp.71-82, August 1999.
• Toshinori Sato, Combining Data Value Prediction with Data Address Prediction, 10th Joint Symposium on Parallel Processing (JSPP), pp.111-118, June 1999 (In Japanese).
• Toshinori Sato, Profile-based Selection of Load Value and Address Predictors, International Symposium on High Performance Computing (ISHPC), pp.17-28, May 1999. Distinguished Paper Award
• Toshinori Sato, Reducing Miss Penalty of Load Value Prediction using Load Address Prediction, 4th Australasian Computer Architecture Conference (ACAC) as a part of Australasian Computer Science Week (ACSW), pp.123-134, January 1999.
• Toshinori Sato, First Step to Combining Control and Data Speculation, 2nd International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA), pp.53-60, October 1998.
• Toshinori Sato, Load Value Prediction using Two-Hop Reference Address Renaming, 4th International Conference on Computer Science and Informatics (CS&I) as a constituent of 4th Joint Conference on Information Sciences (JCIS), Vol.3, pp.225-228, October 1998.
• Toshinori Sato, Data Dependence Speculation using Data Address Prediction and its Enhancement with Instruction Reissue, EUROMICRO Conference, Workshop on Digital System Design: Architectures, Methods and Tools (DSD), pp.285-292, August 1998.
• Toshinori Sato, Analyzing Overhead of Reissued Instructions on Data Speculative Processors, Workshop on Performance Analysis and its Impact on Design (PAID) held in conjunction with 25th International Symposium on Computer Architecture (ISCA), June 1998.
• Toshinori Sato, Preliminary Evaluation of an Instruction Reissue Mechanism, 10th Joint Symposium on Parallel Processing (JSPP), pp.145, June 1998 (in Japanese).
• Toshinori Sato, Load Value Prediction using Reference Address Renaming, 10th Joint Symposium on Parallel Processing (JSPP), pp.15-22, June 1998 (in Japanese).
• Toshinori Sato, Data Dependence Path Reduction with Tunneling Load Instructions, International Symposium on High Performance Computing (ISHPC), pp.119-130, November 1997.
• Toshinori Sato, Speculative Resolution of Ambiguous Memory Aliasing, 1st International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA), pp.17-26, October 1997.
• Toshinori Sato, NCB: A Mechanism for Improving Instruction Fetching Efficiency, 9th Joint Symposium on Parallel Processing (JSPP), pp.221-228, May 1997.
• Toshinori Sato, Yukio Ootaguro, Masato Nagamatsu, Haruyuki Tago, Evaluation of Architecture-level Power Estimation for CMOS RISC Processors, IEEE Symposium on Low Power Electronics (SLPE), pp.44-45, October 1995.
• Toshinori Sato, Masato Nagamatsu, Haruyuki Tago, Power and Performance Simulator:ESP and its Application for 100MIPS/W Class RISC Design, IEEE Symposium on Low Power Electronics (SLPE), pp.46-47, October 1994.
• Toshinori Sato, Hidetoshi Onodera, Keikichi Tamaru, Automatic Generation of Layout Description for Analog Module Generators, International Workshop on Layout Synthesis, Vol.2, pp.193-205, May 1992.
• Ryousuke Okuda, Toshinori Sato, Hidetoshi Onodera, Keikichi Tamaru, An Efficient Algorithm for Layout Compaction Problem with Symmetry Constraints, International Conference on Computer-Aided Design (ICCAD), pp.148-151, November 1989.

Technical reports

• Toshinori Sato, Akihiro Chiyonobu, Exploiting Typical Delays to Boost Instruction Collapsing, IEICE Technical Report CPSY2005-36, pp.19-24, December 2005 (in Japanese).
• Seiichiro Fujii, Akihiro Chiyonobu, Toshinori Sato, Preliminary Evaluation on Correlation between Instruction and Data Criticality, IEICE Technical Report CPSY2005-28, pp.7-12, December 2005 (in Japanese).
• Mikio Yamahara, Kazuhiro Mima, Toshinori Sato, Fast Fault Detection Circuit for Constructive Timing Violation, IPSJ Kyushu Chapter Symposium, March 2005 (in Japanese).
• Hidenori Sato, Toshinori Sato, Yuu Tanaka, Power Reduction of Chip-Multiprocessor using Thread-level Parallelism, The 67th Annual Convention IPS Japan, 1-pp.139-140, March 2005 (in Japanese).
• Daisuke Morishita, Toshinori Sato, A Study on Instruction Placement Problem for Tiled Processors, The 67th Annual Convention IPS Japan, 1-pp.129-130, March 2005 (in Japanese).
• Toshinori Sato, Towards Zero-Performance-Loss Microarchitecture for Transient Faults Tolerance, IEICE Technical Report CPSY2004-60, pp.73-78, December 2004 (in Japanese).
• Koichiro Tanaka, Toshinori Sato, Itsujiro Arita, Development of a C-Based Co-Design Environment for an FPGA/CPU Platform, IPSJ SIG Notes 2004-SLDM-117-7, pp.37-42, December 2004 (in Japanese).
• Akihiro Chiyonobu, Toshinori Sato, Using Dynamic Information of Instruction Criticality for Low Power, IPSJ SIG Notes 2004-ARC-159-29, pp.169-174, July 2004 (in Japanese).
• Kazuhiro Mima, Toshinori Sato, Reducing Hardware Cost in Fault Detection Mechanism for Constructive Timing Violation, IPSJ SIG Notes 2004-ARC-159-4, pp.19-24, July 2004 (in Japanese).
• Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato, A Leakage-Energy-Reduction Technique for Highly-Associative Caches in Embedded Systems, ACM SIGARCH Computer Architecture News, Vol. 32, No. 3, pp.50-54, June 2004.
• Yuu Tanaka, Toshinori Sato, Takenori Koushiro, A Simulation Study on Low-Power Chip-Multiprocessor for Intelligent Mobile Devices, IPSJ Kyushu Chapter Symposium, CD-ROM, March 2004 (in Japanese).
• Akihiro Chiyonobu, Toshinori Sato, Exploiting Instruction Criticality for Low-power Cache Memory Architecture, IPSJ Kyushu Chapter Symposium, CD-ROM, March 2004 (in Japanese).
• Yihei Hayashi, Koichiro Tanaka, Toshinori Sato, Improvements to a SpecC-Based Design Environment for Dynamic and Partial Reconfiguration of FPGAs, 2nd IEICE Workshop on Reconfigurable Systems, pp.3-9, November 2003 (in Japanese).
• Kohtaro Hashimoto, Yuhei Hayashi, Koichiro Tanaka, Toshinori Sato, Design of Multi-Functional Memory Based on FPGAs for DSPs, IPSJ SIG Notes 2003-SLDM-111-9, pp.45-50, October 2003 (in Japanese).
• Yukihide Hayashida, Yihei Hayashi, Koichiro Tanaka, Toshinori Sato, Example of a Reconfigurable System with the FPGA Allowing Partial Run-Time Reconfiguration, 1st IEICE Workshop on Reconfigurable Systems, pp.227-234, September 2003 (in Japanese).
• Toshinori Sato, Daisuke Morishita, Tetsuya Hamada, Seiichiro Fujii, On History-Directed Adaptable Processor Architectures, 1st IEICE Workshop on Reconfigurable Systems, pp.7-13, September 2003 (in Japanese).
• Akihiro Chiyonobu, Toshinori Sato, On Dynamic Identification of Instruction Criticality, IPSJ SIG Notes 2003-ARC-154-1, pp.1-6, August 2003 (in Japanese).
• Takenori Koushiro, Toshinori Sato, Itujiro Arita, A Trace-Level Value Predictor for Contrail Processors, ACM SIGARCH Computer Architecture News, Vol. 31, No. 3, pp.42-47, June 2003.
• Jun Tachikawa, Kenichiro Fukuda, Takanori Hira, Yoshimasa Ohnishi, Toshinori Sato, Hiroshi Koide, T-SDSM: Task-based Software Distributed Shared Memory based on Task-Parallel Processing Framework, IPSJ SIG 2003-HPC-94-3, pp.13-18, June 2003 (in Japanese).
• Asami Tanino, Toshinori Sato, Itsujiro Arita, HDL Design of ALU based on Constructive Timing Violation Technique and its Evaluation, IEICE Technical Report ICD2002-212, pp.7-12, March 2003 (in Japanese).
• Takenori Koushiro, Toshinori Sato, Itujiro Arita, Energy Reduction by Dividing Stream Using Value Prediction, IPSJ SIG Notes 2002-ARC-150-18, pp.95-100, November 2002 (in Japanese).
• Toshinori Sato, Itsujiro Arita, A Fault-Tolerance Mechanism for Microprocessors Utilizing Instruction Redundancy, IEICE Technical Report DC2002-36, pp.13-18, November 2002 (in Japanese).
• Akihiro Chiyonobu, Toshinori Sato, Itsujiro Arita, A Proposal of Critical Path Predictors for Low Power Processor Architecture, IPSJ SIG Notes 2002-ARC-149-2, pp.7-12, August 2002 (in Japanese).
• Yuhei Hayashi, Yuichi Iwaya, Koichiro Tanaka, Toshinori Sato, Itsujiro Arita, Construction of Processing Environment with FPGAs and DSPs, IEICE Technical Report VLD2002-59, pp.19-24, June 2002 (in Japanese).
• Kazuhiro Miwa, Koichiro Tanaka, Toshinori Sato, Itsujiro Arita, Design of KERNEL1 System for Computer Education, The 64th Annual Convention IPS Japan, 1-pp.43-44, March 2002 (in Japanese).
• Kentaro Sako, Koichiro Tanaka, Toshinori Sato, Itsujiro Arita, Implementation of KERNEL2 System for OS Development Education, The 64th Annual Convention IPS Japan, 1-pp.45-46, March 2002 (in Japanese).
• Toshinori Sato, Itsujiro Arita, Reducing Hardware Budget of Data Value Predictors by Exploiting Locality on 1-bit Values, IPSJ SIG Notes 2002-ARC-146-12, pp.67-72, February 2002 (in Japanese).
• Yuichi Iwaya, Yuhei Hayashi, Koichiro Tanaka, Toshinori Sato, Itsujiro Arita, Signal Processing Using the System with Both FPGAs and DSPs, Electronic Design and Solution Fair (EDSF), pp.31-39, January 2002 (in Japanese).
• Kou Morita, Toshiyuki Yamamoto, Toshinori Sato, Itsujiro Arita, The KIT COSMOS Processor: A Case Study on Optimizing Hot Spots, IEICE Technical Report CPSY2001-86, pp.39-46, January 2002 (in Japanese).
• Toshinori Sato, Itsujiro Arita, Contrail Processors for Converting High-Performance into Energy-Efficiency, IEEE Computer Society Technical Commitee on Computer Architecture Newsletter, 2001.
• Akihiko Hamano, Kiichi Sugitani, Toshinori Sato, Itsujiro Arita, Influence of Optimization Levels on Data Speculation, IPSJ SIG Notes 2001-ARC-144-22, pp.123-128, July 2001 (in Japanese).
• Kiichi Sugitani, Toshinori Sato, Itsujiro Arita, HDL Design and its Evaluation of the Low Power Consumption Architecture for Microprocessors, IPSJ SIG Notes 2001-ARC-144-28, pp.159-164, July 2001 (in Japanese).
• Toshinori Sato, Itsujiro Arita, Refining a Fault-Tolerance Mechanism for Microprocessors, IEICE Technical Report FTS2001-21, pp.25-31, July 2001 (in Japanese).
• Toshinori Sato, Itsujiro Arita, Improving Energy Efficiency via Timing Fault Tolerance, IEICE Technical Report VLD2001-05, pp.31-36, May 2001 (in Japanese).
• Toshiyuki Yamamoto, Toshinori Sato, Itsujiro Arita, The KIT COSMOS Processor: Preliminary Study on Characterizing Hot Spots, IEICE Technical Report CPSY2000-61, pp.11-16, November 2000 (in Japanese).
• Toshinori Sato, Itsujiro Arita, Reducing Hardware Budget of Data Value Predictors by Exploiting Frequent Value Locality, IEICE Technical Report CPSY2000-62, pp.17-22, November 2000 (in Japanese).
• Toshinori Sato, Yusuke Nakamura, Itsujiro Arita, Simplified Wakeup Logic for Large Instruction Windows, IEICE Technical Report ICD2000-144, pp.107-112, November 2000 (in Japanese).
• Toshinori Sato, Itsujiro Arita, Reducing Hardware Budget of Data Value Predictors Using Partial Resolution, IEICE Technical Report CPSY2000-3, pp.15-22, April 2000 (in Japanese).
• Jun Tachikawa, Yuji Kuge, Tomohiro Oohama, Koichiro Tanaka, Toshinori Sato, Itsujiro Arita, Design of a Cluster Computing System with Distributed Shared Memory Using PCI-Card Implemented with FPGAs, IEICE Technical Report CPSY99-116, pp.77-84, January 2000 (in Japanese).
• Toshinori Sato, Itsujiro Arita, The KIT COSMOS Processor: Background and Rationale, IEICE Technical Report CPSY99-115, pp.69-76, January 2000 (in Japanese).
• Toshinori Sato, Itsujiro Arita, Evaluation of Variable Latency Pipeline Structure on ILP Processors, IPSJ SIG Notes 99-ARC-135-6, pp.39-44, November 1999 (in Japanese).
• Toshinori Sato, Decoupling Instruction Reissue and Scheduling Mechanisms, IPSJ SIG Notes 99-ARC-133-4, pp.19-24, May 1999 (In Japanese).
• Toshinori Sato, Enhancing Instruction Fetch Width by Grouping Multiple Basic Blocks, IPSJ SIG Notes 97-ARC-125-18, pp.103-108, August 1997.
• Toshinori Sato, Data Dependence Speculation Combining Memory Disambiguation with Address Prediction, IPSJ SIG Notes 97-ARC-125-1, pp.1-6, August 1997.
• Toshinori Sato, Yukio Ootaguro, Masato Nagamatsu, Haruyuki Tago, Architectural-level Power Estimation for CMOS RISC Processors, IPSJ SIG Notes 95-ARC-115-12, pp.71-76, December 1995 (in Japanese).
• Toshinori Sato, Masafumi Takahashi, Hiroshige Fujii, Takeshi Yoshida, Studies on Routing Method for Massively Parallel Processors, The 46th Annual Convention IPS Japan, 6-pp.63-64, 1993 (in Japanese).
• Masafumi Takahashi, Takeshi Yoshida, Toshinori Sato, Hiroyuki Takano, Evaluation of a Cache Memory with a Prefetch Mechanism for High Performance Processors, IEICE Technical Report CPSY93-49, pp.33-38, 1993 (in Japanese).
• Hiroto Fukuhisa, Nobuhiro Ide, Yoshihisa Kondo, Takeshi Yoshida, Hiroyuki Takano, Toshinori Sato, Masato Nagamatsu, Junji Mori, Itaru Yamazaki, Kiyoji Ueno, Floating-point Processing Unit for High Performance Superscalar Processor, IEICE Technical Report CPSY92-84, pp.81-88, 1992 (in Japanese).
• Toshinori Sato, Hidetoshi Onodera, Keikichi Tamaru, A Method for Module Generator Development, IEICE Technical Report VLD90-78, pp.15-22, November 1990 (in Japanese).
• Toshinori Sato, Hidetoshi Onodera, Keikichi Tamaru, A Method for Module Generator Development, 1990 Autum Natl. Conv. Rec. IEICE Japan, No. A-57, 1-pp.57, 1990 (in Japanese).
• Toshinori Sato, Ryosuke Okuda, Hidetoshi Onodera, Keikichi Tamaru, An Algorithm for Symbolic Layout Compaction with Symmetry Constraints, 1989 Autum Natl. Conv. Rec. IEICE Japan, No. A-96, 1-pp.99, 1989 (in Japanese).
• Ryosuke Okuda, Toshinori Sato, Hidetoshi Onodera, Keikichi Tamaru, An Algorithm for Symbolic Layout Compaction with Symmetry Constraints, IEICE Technical Report VLD89-40, pp.17-24, July 1989 (in Japanese).