Toshinori Sato toshinori dot sato at computer dot org http://www.cis.fukuoka-u.ac.jp/~tsato EDUCATION Ph.D in Electronic Engineering, Kyoto University, Japan, January 1999. M.S. in Electronic Engineering, Kyoto University, Japan, March 1991. B.S. in Electronic Engineering, Kyoto University, Japan, March 1989. EXPERIENCE Lecturer, Nagoya University, Nagoya Japan, Graduate School of Engineering (April 2006 - present). - Having a course on microprocessor architecture. Lecturer, the University of Electro-Communications, Chofu Japan, Graduate School of Information Systems (April 2006 - present). - Having a course on parallel processing. Professor, Kyushu University, Fukuoka Japan, System LSI Research Center (January 2006 - present). - Conducting microarchitecture research, especially on low power design. - Having a course on embedded systems. Lecturer, Kyushu Institute of Technology, Iizuka Japan, Department of Artificial Intelligence (January 2006 - present). - Having a course on microprocessor architectures. - Having a course on digital systems and semiconductor designs. Lecturer, Kagoshima University, Kagoshima Japan, Department of Information and Computer Science (April 2002 - present). - Having a course on advanced microprocessor architectures, including high-performance processors and low-power processors. Associate professor, Kyushu Institute of Technology, Iizuka Japan, Center for Microelectronic Systems (February 2001 - December 2005). - Conducting microarchitecture research, especially on low power design. Associate professor, Kyushu Institute of Technology, Iizuka Japan, Department of Artificial Intelligence (October 1999 - December 2005). - Having a course on microprocessor architectures. - Having a course on advanced microprocessor architectures, including high-performance processors and low-power processors. - Having a course on digital systems and semiconductor designs. - Having an experiment on processor design using Verilog-HDL. - Having an experiment on hardware/software partitioning using DSP and FPGA. - Having a seminar on computer systems for citizens outside university. - Having a seminar on modern microprocessor systems for citizens outside university. Lecturer, Utsunomiya University, Utsunomiya, Japan, Faculty of Information Science (September 1999). - Had a course on advanced microprocessor architectures, including multi-threading processors and processors in memory. Engineer, Toshiba Corporation, Kawasaki, Japan, Microelectronics Engineering Laboratory (April 1996 - September 1999) - Designed an embedded microprocessor system, called EmotionEngine, for PlayStation2 game console. I was responsible for register transfer (RT) level designs of its 2 vector units (VU0 and VU1) and floating- point unit (FPU). I had also done some verifications at several levels of the design process. - Designed an embedded microprocessor, called TX-39 (erstwhile R3900). TX-39 was an embedded microprocessor with low power and high performance for the use in PDAs. It had a compatibility with MIPS-II instruction set architecture. Researcher, Toshiba Corporation, Kawasaki, Japan, ULSI Research Laboratories (April 1991 - March 1996) - Developed a cycle accurate simulator of TX-39 mentioned above, which was called ESP (Early design Stage Power and performance simulator). It executed MIPS-II binary codes and estimated power consumption at the microarchitecture level. Papers describing the simulator presented at Symposia on Low Power Electronics (SLPE) 1994 and 1995 were widely referred. - Investigated single chip multiprocessor (CMP) architectures. Our group was one of the pioneers on CMP research. Its cache controller was described in the paper presented at HPCA'96 (Unfortunately, my name was not included in the author list.). - Designed a routing controller for 2D-torus network at the RT level. The routing controller was for a massively parallel processor (MPP) system including the single chip multiprocessors mentioned above. Wormhole routing scheme was implemented. - Developed an interconnection network simulator including the routing controller mentioned above. The interconnection network simulator was attached with a single chip multiprocessor simulator, and constructed the MPP system simulator. - Implemented a multiprocessor system consisting of Transputers. - Verified an FPU for a SPARC-compatible superscalar processor at the RT level. Its performance was 320 MFLOPS. Assistant software engineer, Maruhachi, Kyoto, Japan (April 1990 - March 1991). - Developed a design entry and a database system for Japanese kimonos (traditional cloths). HONORS - Best Paper Award of Symposium on Advanced Computing Systems and Infrastructures, June 2007. - IPSJ Yamashita SIG Research Award, November 2003. - IP Award of Nikkei Business Publishing, Inc., May 2000. - Best Paper Award of IPS Japan, May 2000. - Distinguished Paper Award of International Symposium on High Performance Computing, May 1999. - Achievement Award of Toshiba ULSI Research Laboratories, April 1995. PATENTS Toshinori Sato, "Power management device," Japan Patent JP2003-125394, filed, April 30, 2003. Toshinori Sato, "Cache memories and method for reducing power of cache memories," Japan Patent JP2003-118596, filed, April 23 2003. Toshinori Sato, "Instruction scheduling system of a processor," US Patent US6643767, issued, November 4 2003. Toshinori Sato, "Processor provided with a data value predictor and a branch prediction circuit," US Patent US6516409, issued, February 4 2003. Toshinori Sato, "Cache memories," Japan Patent JP2002-295239, filed, October 8 2002. Toshinori Sato, "Speculative execution of a load instruction by associating the load instruction with a previously executed store instruction," US Patent US6415380, issued, July 2 2002. Toshinori Sato, "Command scheduling device for processors," Japan Patent JP2001-209535, published, August 3 2001. Toshinori Sato, "Method of and apparatus for supplying multiple instruction strings whose addresses are discontinued by branch instructions," US Patent US6119220, issued, September 12 2000. Toshinori Sato, "Processor and branch prediction unit," Japan Patent JP2000-132390, published, May 12 2000. Toshinori Sato, "Instruction scheduling device for processor," Japan Patent JP10-259295, published, September 24 1999. Toshinori Sato, "Data supplying device for processor," Japan Patent JP10-212788, published, August 6 1999. Toshinori Sato, "Pipelined Microprocessor and load address prediction method therefore," US Patent US5903768, issued, May 11 1999. Toshinori Sato, "Method for supplying instruction of processor and device therefore," Japan Patent JP10-214188, published, August 11 1998. Toshinori Sato, "Method and apparatus for calculating power consumption of integrated circuit," US Patent US5754435, issued, May 19 1998. Toshinori Sato, "Microprocessor and its load address processing method," Japan Patent JP09-134287, published, May 20 1997. Toshinori Sato, "Compiler," Japan Patent JP09-044362, published, February 14 1997. Toshinori Sato, "Method and device for calculating power consumption of integrated circuit," Japan Patent JP08-044788, published, February 12 1996. Hiroyuki Takano, Toshinori Sato, "Parallel computers," Japan Patent JP07-191947, published, July 28 1995. Toshinori Sato, "Inter-processor communications controller for parallel computer," Japan Patent JP06-243116, published, September 2 1994. Hiroshige Fujii, Takeshi Yoshida, Toshinori Sato, Masafumi Takahashi, "Parallel computer," Japan Patent JP06-068053, published, March 11 1994. PUBLICATIONS See http://www.slrc.kyushu-u.ac.jp/~tsato/papers.html . PROFESSIONAL ACTIVITIES Associations - Association for Computing Machinery (ACM) and ACM SIGARCH. - Institute of Electrical and Electronics Engineers (IEEE), IEEE Computer Society, and IEEE Solid-State Circuits Society. - Information Processing Society of Japan (IPSJ) and IPSJ SIGARC. Board members of SIGARC (2000 - 2004) and SIGSLDM (2001 - 2005). - Institute of Electronics, Information and Communication Engineers (IEICE). Editorship - Editor, IPSJ Transactions on Advanced Computing Systems (2002 - 2006) - Editor, IPSJ Transactions on High Performance Computing Systems (2002) - Guest editor, Special issue on "System Development" of IEICE Transactions on Information and Systems (2004) - Guest editor, Special issue on "Parallel Processing" of Journal of IPSJ (2001, 2000) Conferences - Program Track Chair of Symposium on Advanced Computing Systems and Infrastructures (2008) - Publication Chair of International Workshop on Advanced Low Power Systems (2007) - Poster Chair of International Symposium on Low-Power and High-Speed Chips (2007 - 2008) - Program Chair of International Workshop on Advanced Low Power Systems (2006) - Lecture Co-Chair of International Symposium on Low-Power and High- Speed Chips (2003, 2002) - Treasury Co-Chair of International Symposium on High Performance Computing (2000) - Organizing committee member of Symposium on Advanced Computing Systems and Infrastructures (2007) - Organizing committee member of Summer United Workshop on Parallel, Distributed, and Cooperative Processing (2004 - 2006) - Organizing committee member of Design Automation Symposium (2004) - Organizing committee member of International Symposium on High Performance Computing (2002, 2000) - Organizing committee member of Joint Symposium on Parallel Processing (2000) - Program committee member of International Conference on Supercomputing (2008) - Program committee member of Design, Automation & Test in Europe Conference and Exhibition (2008) - Program committee member of International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (2007) - Program committee member of International Conference on Parallel and Distributed Computing and Networks (2008, 2007) - Program committee member of International Symposium on Microarchitecture (2005) - Program committee member of Workshop on Memory Performance: Dealing with Applications, Systems and Architecture (2005 - 2007) - Program committee member of International Conference on Parallel Architectures and Compilation Techniques (2004) - Program committee member of Workshop on Synthesis and System Integration of Mixed Information Technologies (2007, 2006, 2004) - Program committee member of International Symposium on Low-Power and High-Speed Chips (2007, 2002 - 2005) - Program committee member of Symposium on Advanced Computing Systems and Infrastructures (2007, 2003 - 2005) - Program committee member of Joint Symposium on Parallel Processing (2001, 2000) - Session chair of Pacific Rim International Symposium on Dependable Computing (2006) - Session chair of International Workshop on Advanced Low Power Systems (2006) - Session chair of International Symposium on Microarchitecture (2005) - Session chair of Workshop on Synthesis and System Integration of Mixed Information Technologies (2004) - Session chair of International Conference on Parallel Architectures and Compilation Techniques (2004) - Session chair of International Symposium on Integrated Circuits, Devices & Systems (2004) - Session chair of International Symposium on High Performance Computing (2005, 2003) - Session moderator of Asia and South Pacific Design Automation Conference (2001) - Session chair of Summer United Workshop on Parallel, Distributed, and Cooperative Processing (2003, 2001) - Session chair of International Symposium on Low-Power and High-Speed Chips (2003) - Session chair of Design Gaia (2002, 1999) - Session chair of International Conference on Software Engineering, Artificial Intelligence, Networking & Parallel/Distributed Computing (2001) - Session chair of Joint Symposium on Parallel Processing (2000) Review - IEEE Transactions on Computers. - IEEE Transactions on Parallel and Distributed Systems. - IEEE Computer - ACM Transaction on Design Automation of Electronic Systems. - IEE Proceedings on Computers and Digital Techniques. - IEE Electronics Letters. - Journal of Systems Architecture. - Journal of Embedded Computing. - International Journal of High Performance Computing and Networking. - International Journal of Computers and Their Applications. - Journal of Information Science and Engineering. - Journal of Circuits, Systems, and Computers. - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. - IEICE Transactions on Communications. - IEICE Transactions on Electronics. - IEICE Transactions on Information and Systems. - Journal of IPSJ. - IPSJ Transactions on Advanced Computing Systems. - IPSJ Transactions on High Performance Computing Systems. - IPSJ Transactions on Mathematical Modeling and its Applications. - ETRI Journal. - Design Automation Conference (2008, 2009) - Asia and South Pacific Design Automation Conference (2008) - International Symposium on System Synthesis (2007) - International Conference on Hardware-Software Codesign and System Synthesis (2007) - World Multi-Conference on Systemics, Cybernetics and Informatics (2007) - International Symposium on VLSI Design, Automation & Test (2007) - International Symposium on Circuits and Systems (2007) - International Conference on Parallel and Distributed Computing and Networks (2007) - International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (2006) - International Workshop on Advanced Low Power Systems (2006) - International Symposium on Computer Architecture (2006) - Workshop on Memory Performance: Dealing with Applications, Systems and Architecture (2005 - 2008) - International Conference on High Performance Embedded Architectures and Compilers (2005) - International Symposium on Microarchitecture (2005) - International Symposium on Low Power Electronics and Design (2005) - International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (2004) - Workshop on Synthesis and System Integration of Mixed Information Technologies (2004-2007) - International Midwest Symposium on Circuits and Systems (2004) - International Conference on Parallel Architectures and Compilation Techniques (2004) - International Conference on Supercomputing (2006, 2004, 2001, 2000) - Symposium on Advanced Computing Systems and Infrastructures (2003 - 2008) - International Conference on Computer Applications in Industry and Engineering (2003) - International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (2003) - Forum on Information Technology (2004, 2003) - International Conference on Field Programmable Logic and Applications (2003) - Symposium on High Performance Computing and Computing Science (2003) - International Symposium on Low-Power and High-Speed Chips (2002 - 2005) - International Conference on Parallel and Distributed Computing, Applications and Technologies (2002) - Joint Symposium on Parallel Processing (2002, 2001, 2000, 1999) - International Symposium on High Performance Computing (2002, 2000, 1999) - Pacific Rim International Symposium on Dependable Computing (2001) - International Conference on Parallel Processing (2000) - International Solid State Circuit Conference (2000, 1996) - Hot Chips (1999) - International Conference on Computer-Aided Design (1997) Seminars - University of Tokyo, "Low-Power and Dependable Processors," July 2006. - Kyushu University, "Speculation," August 2002. - Institute of Systems & Information Technologies/KYUSHU, "Value Predictions," July 2000. - Center of Iizuka Research & Development, "Deep Sub-micron Design," December 1999. - Aizu University, "Value Predictions," June 1999. - Stanford University, "Single Chip Multiprocessors," October 1995. - University of California at Irvine, "Power Estimation," October 1994. - University of California at Los Angeles, "Power Estimation," October 1994. Panels - International SoC Design Conference, "The Future of Digital Device / SoC Industry - Are We on the Right Way?", October 2007. - 12th Asia and South Pacific Design Automation Conference, "Designers' Forum: Top 10 Design Issues," January 2007. - International Workshop on Innovative Architectures, "Future Directions of Microarchitecture," January 2003. - International Symposium on High Performance Computing, "Cooperation between Industry and Academia," May 1999. PERSONAL INFORMATION Date of birth: March 1, 1966. Citizenship: Japan Married with 1 child