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Recent Highlights
- Ken Yano, Takanori Hayashida, and Toshinori Sato,
Improving Timing Error Tolerance without Impact on Chip Area and
Power Consumption,
15th International Symposium on Quality Electronic Design,
pp.389-394, March 2013.
- Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, and Takanori Hayashida,
A Selective Replacement Method for Timing-Error-Predicting Flip-Flops,
Journal of Circuits, Systems and Computers, Vol. 21, No.6, 14 pages,
November 2012.
- Ken Yano, Takanori Hayashida, and Toshinori Sato,
Analysis of SER Improvement by Radiation Hardened Latches,
18th IEEE Pacific Rim International Symposium on Dependable Computing,
pp.89-95, November 2012.
- Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, and Takanori Hayashida,
Guidelines for Mitigating NBTI Degradation in On-chip Memories,
12th International Symposium on Communications and Information Technologies,
pp.827-832, October 2012.
- Yoshimi Shibata, Takanori Hayashida, Toshinori Sato,
and Shinya Takahashi,
Simultaneous Dynamic and Static Power Reduction Utilizing Power
Heterogeneous Functional Units,
27th International Technical Conference on Circuits/Systems, Computers
and Communications, 4 pages, July 2012.
Selected Publications
- Toshinori Sato, Yuji Kunitake,
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM,
8th International Symposium on Quality Electronic Design,
pp.539-545, March 2007.
- Toshinori Sato,
Exploiting Instruction Redundancy for Transient Fault Tolerance,
18th IEEE International Symposium on Defect and Fault Tolerance in
VLSI Systems,
pp.547-554, November 2003.
- Toshinori Sato, Itsujiro Arita,
Constructive Timing Violation for Improving Energy Efficiency,
Compilers and Operating Systems for Low Power,
pp.137-153, Kluwer, September 2003.
- Toshinori Sato, Yusuke Nakamura, Itsujiro Arita,
Revisiting Direct Tag Search Algorithm on Superscalar Processors,
Workshop on Complexity-Effective Design,
June 2001.
- Toshinori Sato, Yukio Ootaguro, Masato Nagamatsu, Haruyuki Tago,
Evaluation of Architecture-level Power Estimation for CMOS RISC
Processors,
IEEE Symposium on Low Power Electronics, pp.44-45, October 1995.